mitsubishi semiconductor PS21254-E transfer-mold type insulated type sep. 2001 0.5 0.2 3.25max 1.9 0.05 0.5max 1 0.2 0.6 0.5 irrgulor solder remains detail b (t=0.7) detail a 1.75max 0.5max 0.8 0.2 0.6 0.5 irrgulor solder remains detail c (t=0.7) type name , lot no. heat sink side b c a 2- 4.5 0.2 1 up 2 vp1 3 vufb 4 vufs 5 vp 6 vp1 7 vvfb 8 vvfs 9 wp 10 vp1 11 vpc 12 vwfb 13 vwfs 14 vn1 15 vnc 16 cin 17 cfo 18 fo 19 un 20 vn 21 wn 22 p 23 u 24 v 25 w 26 n (71) 12.8 1 16 1 or 8 0.5 31 0.5 28 0.5 3.8 0.2 13.4 0.5 21.4 0.5 3~5 11.5 0.5 79 0.5 27 2.8(=75.6) 2.8 0.3 67 0.3 10 0.3 10 0.3 10 0.3 20 0.3 12 34 56 78 91011 1213 14 15 16 17 18 19 20 21 22 23 24 25 26 45 terminal code PS21254-E integrated power functions 4th generation (planar) igbt inverter bridge for 3 phase dc-to-ac power conversion. application ac100v~200v three-phase inverter drive for small power motor control. fig. 1 package outlines mitsubishi semiconductor PS21254-E transfer-mold type insulated type integrated drive, protection and system control functions for upper-leg igbt s : drive circuit, high voltage isolated high-speed level shifting, control circuit under-voltage (uv) protection. note : bootstrap supply scheme can be applied. for lower-leg igbt s : drive circuit, control circuit under-voltage protection (uv), short circuit protection (sc). fault signaling : corresponding to a sc fault (low-side igbt) or a uv fault (low-side supply). input interface : 5v line cmos/ttl compatible, schmitt trigger receiver circuit. dimensions in mm
mitsubishi semiconductor PS21254-E transfer-mold type insulated type sep. 2001 z drive circuit cbu cbu+ cbv cbv+ cbw cbw+ (15v line) (5v line) (note 1, 2) v d v nc v nc w ac line input ac line output v u input signal coditioning level shifter drive circuit protection circuit (uv) input signal coditioning input signal coditioning input signal conditioning fo logic protection circuit protection circuit (uv) protection circuit (uv) control supply under-voltage protection drive circuit drive circuit f o cfo p n 1 n fault output (5v line) (note 3, 5) high-side input (pwm) (5v line) (note 1,2) low-side input (pwm) m (note 6) bootstrap circuit for detailed description of the boot-strap circuit construction, please contact mitsubishi electric dip-ipm c z : znr (surge absorber) c : ac filter (ceramic capacitor 2.2~6.5nf) (note : additionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment). c4 c3 c3 : tight tolerance, temp-compensated electrolytic type c4 : 0.22~2 f r-category ceramic capacitor for noise filtering. (note : the capacitance value depends on the pwm control scheme used in the applied system). note1: to prevent the input signals oscillation, an rc coupling at each input is recommended. (see also fig. 6) 2: by virtue of integrating an application specific type hvic inside the module, direct coupling to cpu terminals without any opto-coupler or transformer isolation is possible. (see also fig. 6) 3: this output is open collector type. the signal line should be pulled up to the positive side of the 5v power supply with a pproximately 5.1k ? resistance. (see also fig. 6) 4: the wiring between the power dc link capacitor and the p/n1 terminals should be as short as possible to protect the dip-ipm against catastrophic high surge voltages. for extra precaution, a small film type snubber capacitor (0.1~0.22 f, high voltage type) is recommended to be mounted close to these p and n1 dc power input pins. 5: fo output pulse width should be decided by putting external capacitor between cfo and v nc terminals. (example : cfo=22nf t fo =1.8ms (typ.)) 6: high voltage (600v or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. h-side igbt s l-side igbt s cin (note 4) fig. 3 inrush current limiter circuit level shifter level shifter note1: in the recommended external protection circuit, please select the rc time constant in the range 1.5~2.0 s. 2: to prevent erroneous protection operation, the wiring of a, b, c should be as short as possible. drive circuit drive circuit protection circuit w v u b c v nc cin a p n1 n c r shunt resistor external protection circuit dip-ipm l-side igbt s h-side igbt s sc protection trip level i c (a) t w ( s) 2 0 short circuit protective function (sc) : sc protection is achieved by sensing the l-side dc-bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the rc circuit). when the sensed shunt voltage exceeds the sc trip-level, all the l-side igbts are turned off and a fault signal (fo) is output. since the sc fault may be repetitive, it is recommended to stop the system when the fo signal is received and check the fault. collector current waveform (note 1) (note 2) fig. 2 internal functions block diagram (typical application example) fig. 3 external part of the dip-ipm protection circuit
mitsubishi semiconductor PS21254-E transfer-mold type insulated type sep. 2001 power terminals control terminals tc heat sink boundary dip-ipm heat sink tc 400 20~+100 40~+125 1500 v d = 13.5~16.5v, inverter part t j = 125 c, non-repetitive, less than 2 s (note 2) 60hz, sinusoidal, ac 1 minute, connection pins to heat-sink plate v cc(prot) t c t stg v iso v v v v ma v 20 20 0.5~+5.5 0.5~v d +0.5 15 0.5~v d +0.5 applied between v p1 -v pc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs applied between u p , v p , w p -v pc , u n , v n , w n -v nc applied between f o -v nc sink current at f o terminal applied between cin-v nc control supply voltage control supply voltage input voltage fault output supply voltage fault output current current sensing input voltage v d v db v cin v fo i fo v sc 450 500 600 15 30 43 20~+150 applied between p-n applied between p-n t c = 25 c t c = 25 c, instantaneous value (pulse) t c = 25 c, per 1 chip (note 1) v cc v cc(surge) v ces i c i cp p c t j condition symbol parameter ratings unit supply voltage supply voltage (surge) collector-emitter voltage each igbt collector current each igbt collector current (peak) collector dissipation junction temperature v v v a a w c maximum ratings (t j = 25 c, unless otherwise noted) inverter part condition symbol parameter ratings unit control (protection) part symbol ratings unit self protection supply voltage limit (short circuit protection capability) module case operation temperature storage temperature isolation voltage v c c v rms total system note 1 : the maximum junction temperature rating of the power chips integrated within the dip-ipm is 150 c (@ t c 100 c) however, to en- sure safe operation of the dip-ipm, the average junction temperature should be limited to t j(ave) 125 c (@ t c 100 c). parameter condition note 2 : t c measurement point
mitsubishi semiconductor PS21254-E transfer-mold type insulated type sep. 2001 fault output pulse width on threshold voltage off threshold voltage 16.5 16.5 8.50 1.00 1.2 1.8 0.55 12.0 12.5 12.5 13.0 2.0 4.0 15.0 15.0 0.8 1.2 0.5 1.8 1.4 3.0 2.5 trip level reset level trip level reset level v d v db v foh v fol v fosat v sc(ref) uv dbt uv dbr uv dt uv dr t fo v th(on) v th(off) 2.45 2.60 3.40 1.20 0.80 1.80 1.25 1 10 2.85 4.5 0.067 t dead ma v t j = 25 c t j = 125 c i c = 15a, t j = 25 c i c = 15a, t j = 125 c v ce(sat) v ec t on t rr t c(on) t off t c(off) i ces condition symbol parameter limits inverter igbt part (per 1/6 module) inverter fwd part (per 1/6 module) case to fin, (per 1 module) thermal grease applied r th(j-c)q r th(j-c)f r th(c-f) min. c/w thermal resistance typ. max. unit t j = 25 c, i c = 15a, v cin = 5v condition symbol parameter limits min. typ. max. 0.10 unit electrical characteristics (t j = 25 c, unless otherwise noted) inverter part collector-emitter saturation voltage fwd forward voltage junction to case thermal resistance contact thermal resistance v d = v db = 15v v cin = 0v switching times v cc = 300v, v d = v db = 15v i c = 15a, t j = 125 c, v cin = 5v ? 0v inductive load (upper-lower arm) collector-emitter cut-off current v ce = v ces 1.80 1.90 2.50 0.70 0.10 0.40 0.70 0.35 v s s s s s v v v v v v v v v v ms limits control (protection) part 13.5 13.5 4.9 0.8 0.45 10.0 10.5 10.3 10.8 1.0 0.8 2.5 note 3 : short circuit protection is functioning only at the low-arms. please select the value of the external shunt resistor such that the sc trip- level is less than 25.5 a. 4: fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. the fault output pulse- width t fo depends on the capacitance value of c fo according to the following approximate equation : c fo = 12.2 ? 10 -6 ? t fo [f]. applied between v p1 -v pc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs control supply voltage control supply voltage condition symbol parameter min. typ. max. unit v d = v db = 15v, v cin =5v, v sc = 0v, f o = 10k ? 5v pull-up v sc = 1v, f o = 10k ? 5v pull-up v sc = 1v, i fo = 15ma relates to corresponding input signal for blocking arm shoot-through. 20 c t c 100 c t j = 25 c, v d = 15v (note 3) circuit current fault output voltage arm shoot-through blocking time short circuit trip level supply circuit under-voltage protection t j 125 c c fo = 22nf (note 4) s c/w c/w v v applied between : u p , v p , w p -v pc , u n , v n , w n -v nc ma total of v p1 -v pc , v n1 -v nc v ufb -v ufs , v vfb -v vfs , v wfb -v wfs i d
mitsubishi semiconductor PS21254-E transfer-mold type insulated type sep. 2001 v v v v/ s s khz v v supply voltage control supply voltage control supply voltage control supply variation arm shoot-through blocking time pwm input frequency input on threshold voltage input off threshold voltage applied between p-n applied between v p1 -v pc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs relates to corresponding input signal for blocking arm shoot-through t c 100 c, t j 125 c applied between u p , v p , w p -v pc applied between u n , v n , w n -v nc 400 16.5 16.5 1 v cc v d v db ? v d , ? v db t dead f pwm v cin(on) v cin(off) condition symbol parameter limits min. typ. max. 0 13.5 13.5 1 2.5 unit recommended operation conditions 300 15.0 15.0 15 0~0.65 4.0~5.5 measurement point dip-ipm place to contact a heat sink heat sink heat sink (note 5) 3mm note 5: measurement point of heat-sink flatness mounting screw : m4 weight 19.6n weight 9.8n. 90deg bend (note 5) condition parameter limits mounting torque terminal pulling strength bending strength weight heat-sink flatness min. mechanical characteristics and ratings typ. max. 0.98 10 2 50 unit 1.18 54 1.47 100 n m s times g m eiaj-ed-4701 eiaj-ed-4701
mitsubishi semiconductor PS21254-E transfer-mold type insulated type sep. 2001 fig. 4 the dip-ipm internal circuit dip-ipm u out v out w out v no cfo gnd fo w n v n u n v cc hvic 3 hvic 2 hvic 1 lvic cfo cin cin n w v u p ho in com v b v s v cc ho in com v b v s v cc ho in com v b v s v cc fo w n v n u n w p v pc v p u p v nc v n1 v p1 v p1 v p1 v wfs v vfs v ufs v wfb v vfb v ufb igbt1 igbt2 igbt3 igbt4 igbt5 igbt6 di1 di2 di3 di4 di5 di6
mitsubishi semiconductor PS21254-E transfer-mold type insulated type sep. 2001 error output fo output current ic(a) control supply voltage v d protection circuit state control input a6 a1 a3 a5 a2 reset uv dt uv dr set a4 error output fo sense voltage of the shunt resistor sc reference voltage cr circuit time constant delay output current ic(a) internal igbt gate protection circuit state n-side control input a5 a8 a4 a3 a1 a2 sc reset set a7 a6 fig. 5 timing charts of the dip-ipm protective functions [a] short-circuit protection (n-side only) (for the external shunt resistor and cr connection.) a1. normal operation : igbt on and carrying current. a2. short circuit current detection (sc trigger). a3. hard igbt gate interrupt. a4. igbt turns off. a5. f o timer operation starts : the pulse width of the f o signal is set by the external capacitor c fo . a6. input h : igbt off state. a7. input l : igbt on state. a8. igbt off state. [b] under-voltage protection (n-side, uv d ) a1. normal operation : igbt on and carrying current. a2. under voltage trip (uv dt ). a3. igbt off in spite of control input condition. a4. f o timer operation starts. a5. under voltage reset (uv dr ). a6. normal operation : igbt on and carrying current.
mitsubishi semiconductor PS21254-E transfer-mold type insulated type sep. 2001 cpu 5.1k ? 5v line 1nf 1nf u p ,v p ,w p ,u n ,v n ,w n fo dip-ipm 4.7k ? v pc , v nc (logic) error output fo output current ic(a) control supply voltage v db protection circuit state control input a6 a1 a2 a4 a5 a3 reset uv dbt uv dbr set reset high-level (no fault output) [c] under-voltage protection (p-side, uv db ) a1. control supply voltage rises : after the voltage level reachs uv dbr , the circuits start to operate when the next input is applied. a2. normal operation : igbt on and carrying current. a3. under voltage trip (uv dbt ). a4. igbt off in spite of control input condition, but there is no f o signal output. a5. under-voltage reset (uv dbr ). a6. normal operation : igbt on and carrying current. fig. 6 recommended cpu i/o interface circuit note : rc coupling at each input (parts shown dotted) may change depending on the pwm control scheme used in the application and on the wiring impedances of the application s printed circuit board.
mitsubishi semiconductor PS21254-E transfer-mold type insulated type sep. 2001 ho ho dip-ipm c1: tight tolerance temp - compensated electrolytic type; c2,c3: 0.22~2 f r - category ceramic capacitor for noise filtering c3 c3 c3 c3 c2 c2 c2 c1 c1 c1 ho in in 15v line 5v line 5v line in com com com u out v out w out v no cfo gnd f o w n v n v cc c b a c4(c fo ) cfo r1 c5 shunt resistor cin cin n1 n w v u p v s v s v s v b v b v b v cc v cc v cc fo w n v n u n u n w p v p u p v nc v n1 v pc v p1 v p1 v p1 v wfs v vfs v ufs v wfb v vfb v ufb m c p u u n i t the long wiring of gnd might generate noise on input signals and cause igbt to be malfunctioned. if this wiring is too long, the sc level fluctuation might be larger and cause sc malfunction. if this wiring is too long, short circuit might be caused. fig. 7 typical dip-ipm application circuit example note 1 : to prevent the input signals oscillation, an rc coupling at each input is recommended, and the wiring of each input should be a s short as possible. (less than 2cm) 2: by virtue of integrating an application specific type hvic inside the module, direct coupling to cpu terminals without any opto -coupler or transformer isolation is possible. 3: f o output is open collector type. this signal line should be pulled up to the positive side of the 5v power supply with approxima tely 5.1k ? resistance. 4: f o output pulse width should be decided by connecting an external capacitor between cfo and v nc terminals (c fo ). (example : c fo = 22 nf t fo = 1.8 ms (typ.)) 5: each input signal line should be pulled up to the 5v power supply with approximately 4.7k ? resistance (other rc coupling circuits at each input may be needed depending on the pwm control scheme used and on the wiring impedances of the system s printed circuit board). approximately a 0.22~2 f by-pass capacitor should be used across each power supply connection terminals. 6: to prevent errors of the protection function, the wiring of a, b, c should be as short as possible. 7: in the recommended protection circuit, please select the r 1 c 5 time constant in the range 1.5~2 s. 8: each capacitor should be put as nearby the pins of the dip-ipm as possible. 9: to prevent surge destruction, the wiring between the smoothing capacitor and the p&n1 pins should be as short as possible. appr oxi- mately a 0.1~0.22 f snubber capacitor between the p&n1 pins is recommended.
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